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anujkadyan
January 8th, 2004, 12:24 PM
If there is someone interested in this plz mail me your resume on Anuj.kadyan@wipro.com as I will have to send it through referral.

Best of luck
anuj


The candidate must be M Tech or ME in Electronics / Electronics & Communication / Electronics & Telecommunications Engineering / Microelectronics or MS (EE).

· Class of 2003 only having at least 70% or GPA of 3 out of 4.0.

· Should have an experience in circuit design, analog design or digital design (as part of course work or project/internship). Experience in physical design, familiarity with layout tools like Avant. Knowledge in using Verilog or VHDL, or hardware modeling in C or System C, exposure to EDA tools is preferred.

· Selected candidates will be taken as Project Engineers and would be involved in board/FPGA/ASIC projects. Would be working in ASIC front end design, verification, backend design, analog design, cell library development, system level design, high end FPGA design and implementation activities. Would get an opportunity to work in leading edge 0.13u or below technologies, exposure to integrated product development and also opportunity to work in high speed board designs and complex FPGA designs. Should have good communication and interpersonal skills.




Work Location: Bangalore / Pune


Selection Process will be held in Bangalore only

SHORTLISTED CANDIDATES WILL BE INTIMATED THROUGH EMAIL ABOUT THE TEST DATE AND VENUE;